PESIMDES User guide

Modeling

To model a distributed embedded system with PESIMDES for performance analysis, it is sufficient to write a simple SystemC program that instantiates and connects proper modules of the PESIMDES library. In particular it is necessary to:

  • instantiate the event stream generators
  • instantiate the event sinks
  • instantiate the tasks
  • instantiate the activation buffers
  • instantiate the processing / communication resources
  • assign the tasks to resources
  • link the event generators, tasks, activation buffers and event sinks

In the following we demonstrate the modeling procedure for the example system depicted in the figure below:

The following listing reports the SystemC code that models the depicted system using components of the PESIMDES library.

  1 #include "pesimdes.h"

  3 #define MAXBUFFER 1000

  5 bool verbose = false;


  8 int sc_main (int argc , char *argv[]) {

 10    // initialize the random number generator
 11    srand(-24);


 14    // Module instantiations

 16    // Event stream generators
 17    input_periodic_with_burst_uwj input_generator_1 ("I1",sc_time(20,SC_MS),sc_time(55,SC_MS),
                                                        sc_time(2,SC_MS),"input_trace_1.tra");
 18    input_periodic input_generator_2 ("I2",sc_time(10,SC_MS),"input_trace_2.tra");

 20    // Tasks
 21    task t1("T1",2,"AND",1);
 22    task t2("T2");
 23    task t3("T3");
 24    task t4("T4",2);
 25    task t5("T5");

 27    // Resources
 28    resource_n_tasks_fixed_priority_preemptive cpu_1("CPU1",2);
 29    resource_n_tasks_EDF_preemptive cpu_2("CPU2",2);
 30    resource_n_tasks_fixed_priority_preemptive cpu_3("CPU3",1);

 32    // Event sinks
 33    output_display display_1("O1");
 34    output_display display_2("O2");


 37    // Task mapping
 38    cpu_1.assign_task(t1,0,sc_time(2,SC_MS),1);
 39    cpu_1.assign_task(t2,1,sc_time(1,SC_MS),2);
 40    cpu_2.assign_task(t3,0,sc_time(7,SC_MS),sc_time(18,SC_MS));
 41    cpu_2.assign_task(t4,1,sc_time(3,SC_MS),sc_time(35,SC_MS));
 42    cpu_3.assign_task(t5,0,sc_time(8,SC_MS),1);


 45   // Channel instantiations

 47    // Task activation buffers
 48    my_sc_fifo<event_token> buffer_T1_1(MAXBUFFER);
 49    my_sc_fifo<event_token> buffer_T1_2(MAXBUFFER);
 50    my_sc_fifo<event_token> buffer_T2(MAXBUFFER);
 51    my_sc_fifo<event_token> buffer_T3(MAXBUFFER);
 52    my_sc_fifo<event_token> buffer_T4(MAXBUFFER);
 53    my_sc_fifo<event_token> buffer_T5(MAXBUFFER);

 55    // Dummy buffers for event sinks
 56    sc_fifo<event_token> dummy_buffer_display_1(1);
 57    sc_fifo<event_token> dummy_buffer_display_2(1);


 60    // Port binding

 62    // Stream I1-O1
 63    input_generator_1.out(buffer_T3);
 64    t3.in[0](buffer_T3);
 65    t3.out[0](dummy_buffer_display_1);
 66    display_1.in(dummy_buffer_display_1);

 68    // Stream I2-O2
 69    input_generator_2.out(buffer_T1_1);
 70    t1.in[0](buffer_T1_1);
 71    t1.out[0](buffer_T4);
 72    t4.in[0](buffer_T4);
 73    t4.out[0](buffer_T5);
 74    t4.out[1](buffer_T1_2);
 75    t1.in[1](buffer_T1_2);
 76    t5.in[0](buffer_T5);
 77    t5.out[0](buffer_T2);
 78    t2.in[0](buffer_T2);
 79    t2.out[0](dummy_buffer_display_2);
 80    display_2.in(dummy_buffer_display_2);


 83    // Initial state
 84    set_initial_token(buffer_T1_2,2);


 87    // Start simulation
 88    sc_start(100000,SC_MS);


 91    // Print performance results
 92    cout << "\n Max. observed End-to-End Delay from I2 to O2: " <<
            sc_time_output(display_2.getmaxlatency("I2")) << " (event no. " <<
            display_2.getseqnoofmaxlatency("I2") << ")\n";
 93    cout << "Max. observed Backlog T2: " << buffer_T2.getmaxbacklog() << "\n";

 95    return 0;
 96 }

The instantiation and connection of the various components is straightforward. More documentation about the single constructor calls can be found in the corresponding header files of the library.

Simulation

Once the topology of the system is modeled by instantiating and connecting proper PESIMDES modules, it is necessary to configure the simulation. In particular the following simulation parameters must be set:

Maximum Buffersize

A maximum size for the task activation buffers must be specified (see line 3 of above listing). Note that the buffer size does not influence the behavior of the system, i.e. a full buffer does not block a writing task. In case of a buffer overflow an appropriate exception is raised and the simulation is stopped.

Simulation length

The length of the simulation must be specified as parameter of the sc_start call (see line 88 of above listing), which determines the duration of the SystemC simulation. Note that by this parameter you specify the amount of time to simulate and not the running time of the simulation.

Simulation outputs

In order to obtain the estimations for the requested performance characteristics of the system it is necessary to output the return values of the functions getmaxlatency and getmaxbacklog called on the corresponding components (see lines 92 and 93 of above listing)

Random number generator

Various event generators make use of a random number generator. The corresponding seed value can be set explicitly (see line 11 of above listing). By choosing twice the same seed number the results of a simulation can be reproduced.

Verbose option

It is possible to instruct the PESIMDES components to print to standard output a detailed simulation log. This is done by setting the verbose flag (see line 5 of above listing). The log traces generation, processing and propagation of every single event in the system. Note that the use of the verbose feature may significantly increase the running time of the simulation.